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U2730B
L-Band Down-Converter for DAB Receivers
Description
The U2730B is a monolithic integrated L-band downconverter circuit fabricated in TEMIC Semiconductors' advanced UHF5S technology. It covers all functions of an L-band down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain-control block, an L-band oscillator and a complete frequency syntheziser unit. The frequency syntheziser block consists of an input buffer for the reference frequency signal, a reference divider, an LO divider, a tri-state phase detector, a loop filter amplifier, a lock detector, a programmable charge pump, a test interface and a control interface. Electrostatic sensitive device. Observe precautions for handling.
Features
D D D D D D D D D
Supply voltage: 8.5 V RF frequency range: 1400 MHz to 1550 MHz IF frequency range: 150 MHz to 250 MHz Overall IM3 rejection: > 40 dB Overall gain control range: typ. 30 dB DSB noise figure: 9.5 dB Gain-controlled amplifier Gain-controlled L-band mixer On-chip gain-control circuitry
TH 17 AGC 18 Test interface
internal supply voltage for frequency synthesizer
D On-chip VCO, typical frequency 1261.568 MHz D Internal VCO can be overdriven by an external LO D On-chip frequency synthesizer
- - - - - - Fixed LO divider factor: 2464
Four reference divider factors selectable: 32, 35, 36, 48 Tristate phase detector with programmable charge pump
De-activation of tuning output programmable Lock-status indication Test interface
VCC1 VCC3 VCC4 3 20 28 VCC2 9 Voltage stabilizer GND 6, 7, 8, 21, 22, 23, 24
Block Diagram
IF 19 TMD TRD 10 11
U 26 25 Lock detector 14 13 20k 12
Reference counter
RF NRF
PLCK PD
VCO
RF counter 2464 Tristate phase detector Programmable charge pump (50A / 200A)
CD
32/35/36/48
Control interface 4 VREF 5 15 16 NREF 2 C 27 S
14749
TANK REF
Figure 1. Block diagram
Rev. A1, 20-May-99
1 (12)
Preliminary Information
U2730B
Ordering Information
Extended Type Number U2730B-MFS U2730B-MFSG1 Package SSO28 SSO28 Remarks Tube Taped and reeled according to IEC 286-3
Pin Description
n.c. C VCC1 VREF TANK GND GND GND VCC2 28 VCC4 27 S 26 RF 25 NRF 24 GND 23 GND 22 GND 21 GND 20 VCC3 19 IF 18 AGC 17 TH 16 NREF 15 REF
14828
1 2 3 4 5 6 7 8 9
Pin 1 2 3 4 5 6, 7, 8, 21, 22, 23, 24 9 10 11 12 13 14 15 16 17 18
Symbol n.c. C VCC1 VREF TANK GND
Function Not connected Control input Supply voltage Reference pin of VCO Tank pin of VCO Ground
VCC2 TMD TRD CD PD PLCK REF NREF TH AGC
TMD 10 TRD 11 CD 12 PD 13 PLCK 14
19 20 25 26 27 28
IF VCC3 NRF RF S VCC4
Supply voltage Test output of main divider Test output of reference divider Active filter output Three-state charge pump output Lock-indication output (open collector) Reference divider input Reference divider input (inverted) Threshold voltage of comparator Charge-pump output of comparator, AGC input for amplifier and mixer Intermediate frequency output Supply voltage RF input (inverted) RF input Control input Supply voltage
Figure 2. Pinning
2 (12)
Rev. A1, 20-May-99
Preliminary Information
U2730B
Functional Description
The U2730B-B is an L-band down-converter circuit covering a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain-control circuitry, an L-band oscillator and a frequency synthesizer block. Designed for applications in an DAB receiver, the purpose of this circuit is to down-convert incoming L-band signals in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz which can be handled by a subsequent DAB tuner. A block diagram of this circuit is shown in figure 1.
Voltage-Controlled Oscillator
A voltage-controlled oscillator supplies an LO signal to the mixer. An equivalent circuit of this oscillator is shown in figure 5. In the application circuits figures 3 and 5, a ceramic coaxial resonator is applied to the oscillator's Pins TANK and REF. It should be noted that the Pin REF has to be blocked carefully. Figure 6 shows a different application where the oscillator is overdriven by an external oscillator. In any case, a DC path at a low impedance must be established between the Pins TANK and REF. The output signal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the VCO's frequency on the frequency of a reference signal applied to the Pins REF and NREF. Figure 7 shows the typical phase-noise performance of the oscillator in locked state.
Gain-Controlled Amplifier
RF signals applied to the input Pin RF are amplified by a gain-controlled amplifier. Although the complementary Pin NRF is internally blocked, it is recommended to block this pin additionally by an external capacitor. The gain-control voltage is generated by an internal gaincontrol circuitry. The output signal of this amplifier is fed to a gain-controlled mixer.
Overall Properties of the Signal Path
The overall gain of this circuit amounts 21 dB, the gaincontrol range is about 32 dB.
Gain-Controlled Mixer and Output Buffer
The purpose of this mixer is to down-convert the L-band signal in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered and filtered by a one-pole lowpass filter at a 3-dB frequency of about 500 MHz and then it is fed to the single-ended output Pin IF.
Frequency Synthesizer
The frequency synthesizer block consists of an input buffer for a reference signal, a reference divider, an LO divider to divide the frequency of the internal oscillator, a tristate phase detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control interface and a test interface. The control interface is accessed by two control pins, Pins C and S. The test interface provides test signals which represent output signals of the reference and the LO divider. The purpose of this unit is to lock the frequency, fVCO, of the internal VCO on the frequency, fref, of the reference signal applied to the input Pins REF and NREF by a phase-locked loop according to the following equation: fVCO = SF where: SF = 2464 SFref = scaling factor of reference divider according to the following table Voltage at Pin S (Pin 27) Ground VCC / 2 Open VCC VCC-supply voltage SFref 35 32 48 36 fref / SFref
Gain-Control Circuitry
The purpose of the gain-control circuitry is to measure the signal power, to compare it with a certain power level and to generate control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of this functional block is shown in figure 4. In order to meet this functionality, the output signal of the buffer amplifier is weakly bandpass filtered (transition range about 60 MHz to 550 MHz), rectified, lowpass filtered and fed to a comparator whose threshold can be defined by an external resistor, RTH, at Pin TH. By varying the value of this resistor, a power threshold of about -35 dBm to -25 dBm can be selected. In order to achieve a good intermodulation ratio, it is recommended to keep the power threshold below -30 dBm. An appropriate application is shown in figure 3. Depending on the selection made by the comparator, a charge pump charges or discharges a capacitor which is applied to the Pin AGC. By varying this capacitor, different time constants of the AGC loop can be realized. The voltage arising at the Pin AGC is used to control the gain setting of the gain-controlled amplifier and mixer. By applying an external voltage to the Pin AGC the internal AGC loop can be overdriven.
Rev. A1, 20-May-99
3 (12)
Preliminary Information
U2730B
Reference Divider
Four different scaling factors of the reference divider can be selected by the input Pin S: 32, 35, 36, 48. Starting from a reference oscillator frequency of 16.384 MHz/ 17.92 MHz/ 18.432 MHz/ 24.576 MHz these scaling factors result in an output frequency of the reference divider of 512 kHz. If the input control Pin C is left open (high-impedance state), a test signal which monitors the output frequency of the reference divider appears at the output Pin TRD of the test interface.
Phase Comparator, Charge Pump and Loop Filter
The tristate phase detector causes the charge pump to source or to sink current at the output Pin PD depending on the phase relation of its input signals which are provided by the reference and the RF divider respectively. By means of the control Pin C, two different values of this current can be selected, and furthermore the charge-pump current can be switched off. A high-gain amplifier (output Pin CD) which is implemented to construct a loop filter, as shown in the application circuit, can be switched off by means of the control Pin C. In the application circuit figure 3, the loop filter is completed by connecting the Pins PD and CD by an appropriate RC network. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is detected, the open collector output Pin PLCK is set to HIGH. It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the voltage at the control Pin C is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is de-activated and the logical value of the PLCK output is undefined.
LO Divider
The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in the section `Reference divider', the oscillator's frequency is controlled to be 1261.568 MHz in locked state, the output frequency of the RF divider is 512 kHz. In analogy to the reference divider, a test signal which monitors the output frequency of the RF divider appears at the output Pin TMD of the test interface if the input control Pin C is left open (high-impedance state).
Absolute Maximum Ratings
Parameters Supply voltage RF input voltage Voltage at Pin AGC Voltage at Pin TH Input voltage at Pin TANK (internal oscillator overdriven) Current at IF output Reference input voltage (diff.) Control input voltage PLCK output current PLCK output voltage Junction temperature Storage temperature Pins 3, 9, 20 and 28 Pins 25 and 26 Pin 18 Pin 17 Pin 5 Pin 19 Pins 15 and 16 Pins 1, 2 and 27 Pin 14 Pin 14 Symbol VCC VRF VAGC VTH VTANK IIF REF, NREF C, S IPLCK VPLCK Tj Tstg Value -0.3 to +9.5 750 0.5 to 6 -0.3 to +4.0 1 4.0 1 -0.3 to +9.5 0.5 -0.3 to +5.5 125 -40 to +125 Unit V mVpp V V Vpp mA Vpp V mA V C C
Operating Range
Parameters Supply voltage Ambient temperature Pins 3, 9, 20 and 28 Symbol VCC Tamb Min. 8.0 -40 Typ. 8.5 Max. 9.35 +85 Unit V C
4 (12)
Rev. A1, 20-May-99
Preliminary Information
U2730B
Thermal Resistance
Parameters Junction ambient SSO28 (mod.) Symbol RthJA Value t.b.d. Unit K/W
Electrical Characteristics
Operating conditions: VCC = 8.5 V, Tamb = 25C, application circuit see figure 3, unless otherwise specified Parameters Test Conditions / Pins Supply current (max. gain) pRF = -60 dBm Supply current (min. gain) pRF = -10 dBm Overall characteristics Pin 8 2 Maximum conversion gain pRF = -60 dBm Minimum conversion gain pRF = -10 dBm AGC range Third order 2 tone pRF1 + pRF2 = -6 dBm intermodulation ratio pRF1 + pRF2 = -15 dBm DSB noise figure Maximum gain (50- system) Minimum gain RF input Pin 26 Frequency range Maximum input power dim3 20 dB Input impedance IF output Pin 19 Frequency range Output impedance Voltage standing wave ratio VCO Pin 5 Frequency Phase noise 100 kHz distance, application circuit see figure 5 Minimum input power VCO overdriven, application circuit see figure 6 Maximum input power Frequency synthesizer RF divide factor Reference divide factor Pin S connected to GND Pin S connected to VCC/2 Pin S open Pin S connected to VCC Symbol IS,MAX IS,MIN gc,max gc,min Min. 40 44 18 -14 20 30 Typ. 51 55 21 -11 32 35 40 9.5 30 Max. 62 66 24 -8 Unit mA mA dB dB dB dB dB dB dB MHz dBm W || pF MHz
Dgc
NF
dim3
fin,RF pin,max,RF Zin,RF fout,IF Zout,IF VSWRIF fLO L100kHz pLO,MIN pLO,MAX SF SFref
1400 -6 200 || 1 150 50 2.0 1000 1261.568 -100 -11 -5 2464 35 32 48 36
1550
250
1500
MHz dBc/Hz dBm dBm
Rev. A1, 20-May-99
5 (12)
Preliminary Information
U2730B
Electrical Characteristics (continued)
Operating conditions: VCC = 8.5 V, Tamb = 25C, application circuit see figure 3, unless otherwise specified Parameters REF input REF, NREF Input frequency range Test Conditions / Pins Pins 15 and 16 Pin S connected to GND Pin S connected to VCC/2 Pin S open Pin S connected to VCC Input sensitivity Maximum input signal Input impedance Phase detector Charge-pump current Vrefs Vrefmax Zref Symbol fref Min. 5 17.920 16.384 24.576 18.432 10 2.7k || 2.5 160 40 203 50 240 60 100 0.3 Typ. Max. 50 Unit MHz MHz MHz MHz MHz mVrms mVrms kW || pF
20 300
Single-ended
Output voltage PD Internal reference frequency Typical tuning voltage Pin 12 range Lock indication PLCK Pin 14 Leakage current VPLCK = 5.5 V Saturation voltage IPLCK = 0.5 mA Control inputs C and S Pins 2 and 27 Input voltage Pin connected to GND Pin connected to VCC/2 Pin open Pin connected to VCC Test outputs TMD, TRD Pins 10 and 11 Frequency Pin C open Voltage swing Rload 1 MW, Cload 15 pF, Pin C open
Pin C connected to VCC Pin 13 Pin C connected to GND Pin C connected to VCC/2 Pin 2 open Pin 13
IPD2 IPD1 IPD1,tri VPD fPD Vtune
A A nA V kHz V
512 0.3 5
IPLCK VPLCK,sat VL VM Vopen VH ftest Vtest 0 0.4 VCC open 0.9 VCC 512 400
10 0.5 0.1 VCC 0.6 VCC 1
A V V V V kHz mVpp
6 (12)
Rev. A1, 20-May-99
Preliminary Information
U2730B
Application Circuit
Example: reference divider factor = 35, charge-pump current = 200 mA
VAGC 3.3
8.5V 10n
RF 10n
8.5V
IF
1n 1n
Rth
100p 100p 100p
100p 1n 10n 10n 15
Reference oscillator
28
27
26
25
24
23
22
21
20
19
18
17
16
1 8.5V
2
3
4
5
6
7
8
9
10
11
12
13
14
20k
5V
1n 100p 100p 100p 56p 100k 10n 8.5V 10p Resonator 6.8p 10p BBY51 *) optional components VTune
14750
Lock indication
10n 8.5V
1.5p
47k
1k *) 3.3n
1k *) 3.3n
Figure 3. Application circuit
Rev. A1, 20-May-99
7 (12)
Preliminary Information
U2730B
Equivalent Circuits
Gain- controlled mixer Gain- controlled amplifier VRef1
550MHz IF output 60MHz VRef2
AGC
TH Rth
15001
Figure 4. AGC contol circuit
BBY51 VTune 47k
VCC
1.5p 10p 6.8p Resonator 10p TANK
REF
100p
15002
Resonator: Siemens Matsushita (/4-Resonator) Ceramic Coaxial Resonator 1.6 GHz B69640-G 1607-B412 Notice: The VCO needs a DC-path between TANK and VREF-Pin
Figure 5. VCO circuit
8 (12)
Rev. A1, 20-May-99
Preliminary Information
U2730B
Application Circuit for External LO Signal
With an external LO signal it is possible to overdrive the VCO. In this case, the internal VCO acts as an LO buffer.
ext. LO signal (50 signal gen.) PLO = -10dBm 50 TANK 100p 470nH REF 1n
15003
Figure 6. Application circuit for external LO signal
Phase-Noise Performance
Operating conditions VCC = 8.5 V, Tamb = 25C, application circuit see figure 3, IPD = 200 A, fREF = 17.92 MHz / -10 dBm 10.00 dB / DIV
< -75 dBc/Hz
CENTER 1261.568 MHz RB 100 Hz VB 100 Hz
Figure 7. Phase noise
SPAN 50.00 kHz
Rev. A1, 20-May-99
9 (12)
Preliminary Information
U2730B
Typical Gain Control Charateristics
Operating conditions: VCC = 8.5 V, Tamb = 25C, FRF = 1490 MHz, FLO = 1261.568 MHz
-20 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 -70
-25 Rth=6.8kW -30 Rth=12kW vAGC ( V ) pIF ( dBm)
Rth=18.8kW Rth=6.8kW
-35
Rth=18.8kW
-40 -70
14851
-60
-50
-40
-30
-20
-10
0
14852
-60
-50
-40
-30
-20
-10
0
pRF ( dBm )
pRF ( dBm )
Figure 8. IF output power (Pin 19)
Figure 9. Gain control voltage (Pin 11)
Third Order 2-Tone Intermodulation Ratio (dim3)
Operating conditions: fRF1 = 1490 MHz, fRF2 = 1491 MHz, pRF1 = pRF2 = pRF
50 45 dim3 ( dBc )
Total Supply Current
Operating conditions: RTH = 12 kW, PLL locked, Icp = 200 mA
65.0 62.5 60.0 VS=9.35V
35 30 25 20 -70
Rth=18.8kW Rth=12kW Rth=6.8kW
Is ( mA )
40
57.5 VS=8.5V 55.0 52.5 50 -70
-60
-50
-40
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
14854
14853
pRF ( dBm )
pRF ( dBm )
Figure 10.
Figure 11.
10 (12)
Rev. A1, 20-May-99
Preliminary Information
U2730B
Package Information
Package SSO28
Dimensions in mm
9.10 9.01 5.7 5.3 4.5 4.3
1.30 0.25 0.65 8.45 28 15 0.15 0.05 6.6 6.3 0.15
technical drawings according to DIN specifications
13018
1
14
Rev. A1, 20-May-99
11 (12)
Preliminary Information
U2730B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
12 (12)
Rev. A1, 20-May-99
Preliminary Information

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